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There are two kinds of assertions: Immediate assertions check for a condition at the current simulation time. An immediate assertion is the same as an if. else statement with assertion.
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In systemverilog there are two kinds of assertions: Immediate (assert) and concurrent (assert property). Coverage statements ( cover property ) are concurrent and have the same syntax. Is this a faulty design or a faulty assertion?
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It depends on the design specification! A req (request) should be followed two cycles later by ack (acknowledge). The ack line can be tied. Immediate assertions are executed like a statement in a procedural block and follow simulation event. Writing an assertion helps out to improve debugging time.
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